Integrated circuit with an undervoltage detector

ABSTRACT

An integrated circuit arrangement includes connection terminals, an undervoltage detector, and at least one circuit unit. The connection terminals are configured to receive a supply voltage. The undervoltage detector is coupled between the connection terminals and is configured to compare the supply voltage with a select reference value selected from a first reference value and a second reference value. The second reference value is less than the first reference value. The undervoltage detector is further operable to produce a detector signal on the basis of a result of the comparison. The circuit unit is coupled between the connection terminals, and includes a first operating state with a first drawn current and a second operating state with a second drawn current. The second drawn current exceeds the first drawn current. The select reference value corresponds to an operating state of the at least one circuit unit.

The present invention relates to an integrated circuit with anundervoltage detector.

It is sufficiently well known for integrated circuits to be providedwith undervoltage detectors which serve to identify a drop in a supplyvoltage supplied to the integrated circuit in order to disconnect thecircuit if appropriate or to transfer it to a prescribed “safe” state.

An integrated circuit with connection terminals 11, 12 for applying asupply voltage and an undervoltage detector 20 connected in theintegrated circuit between the supply voltage terminals is shownschematically in FIG. 1. The connection terminals 11, 12 are used tosupply power to further circuit components which are present in theintegrated circuit 1 and which are shown schematically as a circuitblock 30 in FIG. 1. The undervoltage detector 20 is designed to monitorthe supply voltage V1 applied between the connection terminals 11, 12and to disconnect the other circuit components 30, for example, if anundervoltage is detected, i.e. if this voltage drops below a prescribedvalue.

To protect against brief voltage spikes in a supply voltage V+, forexample brought about by electrostatic discharges, it is known practiceto connect integrated circuits to terminals of a supply voltage sourcenot directly but rather via a series resistor. Such a series resistor isdenoted by the reference symbol R in the circuit shown in FIG. 1 and isconnected between one of the connection terminals and a node which is atthe supply voltage V+ relative to a reference-ground potential GND. Incombination with a protective capacitor C connected in parallel with theintegrated circuit 1, this series resistor R prevents brief voltagefluctuations from causing the rms supply voltage V1 for the circuit torise unconditionally as a result of the voltage spike in the supplyvoltage.

For operating states of the circuit 1 in which an increased supplycurrent I1 flows briefly into the circuit, this series resistor R mayresult in the rms supply voltage V1 dropping to a value at which theundervoltage detector 20 responds, however.

To avoid this, the undervoltage detector 20 may be designed such that itreacts to a drop in the rms supply voltage V1 below a prescribedthreshold value only after a time delay. However, this delay alsoprompts a reaction to a drop in the rms supply voltage V1 which resultsfrom a disturbance in the voltage supply only after a time delay.

It is therefore an aim of the present invention to provide an integratedcircuit having an undervoltage detector which is able to react quicklyto a disturbance-related drop in a supply voltage applied to connectionterminals of the integrated circuit.

This aim is achieved by a circuit in accordance with claim 1.Advantageous refinements of the invention are the subject matter of thesubclaims.

The inventive circuit arrangement comprises connection terminals forapplying a supply voltage, an undervoltage detector which is connectedbetween the connection terminals and which produces a detector signal,and at least one load circuit unit which is connected between theconnection terminals and which assumes at least one first operatingstate with a first drawn current or a second operating state with asecond drawn current, which is increased in comparison with that of thefirst operating state. The undervoltage detector is designed to comparethe supply voltage with a first reference value or with a secondreference value, which is smaller than the first reference value,depending on the operating state of the at least one circuit unit, inorder to produce the detector signal.

The detector signal is preferably a binary signal whose signal levelindicates a drop in the supply voltage below the respective referencevalue. Such a drop in the supply voltage below the respective referencevalue is called the fault state below.

If this circuit arrangement uses the operating state of the at least onecircuit unit provided as a load to identify that there is an increaseddrawn current, the supply voltage applied between the connectionterminals is compared with the smaller second reference value. Thislowers the threshold at which it is decided that too low a supplyvoltage is present, and hence that a fault state is present. A drop inthe supply voltage which is caused by a voltage drop across a possiblyprovided series resistor when the circuit unit has an increased drawncurrent is thus not regarded as erroneous and indicated by the detectorsignal until the supply voltage drops below the smaller second referencevalue. In this case, the second reference value can be matched to themaximum current drawn by the load, to the permissible minimum value fora supply voltage which has been applied (via the series resistor), andto the value of a series resistor which is normally used, such that therms supply voltage applied between the connection terminals does notdrop below this second reference value if there is no fault and if theexternally applied supply voltage does not drop below its permissibleminimum value.

The operating state of the load circuit unit can be detected in variousways.

If the integrated circuit arrangement contains, by way of example, anactuation signal which actuates the load circuit unit and which containsinformation about the operating state of this circuit unit or about animminent change to the operating state, this actuation signal can beused in the undervoltage detector to change over the comparisonthreshold. In this case, the actuation signal is used as a forecastsignal for an imminent change to the operating state and hence animminent dip in the supply voltage.

An example of a circuit unit which changes from a first operating statewith a relatively low drawn current to a second operating state with anincreased drawn current as stipulated by an actuation signal is acircuit unit with a power MOSFET and an associated driver circuit. Insuch a circuit, the MOSFET changes its switching state as stipulated byan actuation signal under the actuation of the driver circuit. Thischange in the switching state normally requires an intermittentlyincreased drawn current in the driver circuit until the gate capacitanceof the MOSFET has reversed its charge accordingly.

The load circuit unit may also have a measurement circuit which isactuated by the actuation signal and which starts a measurement routine,which requires an increased drawn current, as stipulated by theactuation signal.

If the integrated circuit arrangement does not contain a suitableactuation signal from which it is possible to take information about theoperating state of the load circuit unit, a further embodiment hasprovision for an operating state detector which is coupled to thiscircuit unit and which produces an operating state signal which isdependent on the operating state and which is supplied to theundervoltage detector. To produce this operating state signal, theoperating state detector can ascertain the current flowing into the loadcircuit unit, for example.

The present invention is explained in more detail below with referenceto figures.

FIG. 1 schematically shows an integrated circuit arrangement with anundervoltage detector based on the prior art.

FIG. 2 shows an inventive integrated circuit arrangement with a loadcircuit unit and an undervoltage detector which assesses a supplyvoltage using a first or a second reference value, depending on anoperating state of the circuit unit.

FIG. 3 shows an implementation example of a voltage source arrangementfor producing a first and a second reference voltage.

FIG. 4 shows an inventive integrated circuit arrangement with a loadcircuit unit which has a power MOSFET and in which an operating statesignal is produced from an actuation signal from the circuit unit.

FIG. 5 shows examples of waveforms for selected signals in a circuitarrangement shown in FIG. 4.

FIG. 6 shows an implementation example of a timer in the undervoltagedetector shown in FIG. 5.

FIG. 7 shows an inventive integrated circuit arrangement with anoperating state detector which is coupled to the load circuit unit andwhich produces an operating state signal by evaluating a drawn currentin the load circuit unit.

FIG. 8 shows a modification of the undervoltage detector shown in FIG.4.

In the figures, unless stated otherwise, components and signals whichhave the same meaning are denoted by the same reference symbols.

FIG. 1 shows a first exemplary embodiment of an inventive integratedcircuit arrangement 1. This circuit arrangement is integrated in asemiconductor chip and can have contact made with it externally viaconnection terminals (not shown in more detail).

The circuit arrangement has supply voltage terminals 11, 12 betweenwhich a supply voltage can be applied. In FIG. 2, V1 denotes an rmssupply voltage for the integrated circuit arrangement, which voltage isapplied between these connection terminals 11, 12. This rms supplyvoltage V1 results from a supply voltage V+ which, in the example, takesreference-ground potential GND as a reference and which is applied tothe supply voltage terminals 11, 12 via a series resistor R. To thisend, a first supply voltage terminal 11 is connected to a positivesupply potential V+ via the series resistor R, and the second supplyvoltage terminal 12 is connected to reference-ground potential GND.

In the integrated circuit arrangement 1, an undervoltage detector 2 isconnected between the supply voltage terminals 11, 12 and is designed todetect an undervoltage, that is to say an excessively small rms supplyvoltage V1, and to provide a detector signal S. Regardless of whether anundervoltage is detected, the detector signal S2 assumes a first or asecond signal level.

The rms supply voltage V1 feeds a load circuit unit 3, which is shownmerely schematically as a circuit block in FIG. 2. This circuit unit,which is subsequently called the load circuit unit, can assume at leasttwo different operating states: a first operating state with a firstdrawn current and a second operating state with a second drawn current,which is increased in comparison with that of the first operating state.The drawn current corresponds to the input current I3 which the circuitunit 3 draws via the supply voltage terminals 11, 12. In this context,it should be noted that “first drawn current” and “second drawn current”are not necessarily to be understood to mean constant drawn currents,but rather that they can also be understood to mean ranges within whichthe input current can vary.

The undervoltage detector 2 is designed to compare the rms supplyvoltage V1 applied between the supply voltage terminals 11, 12 eitherwith a first reference voltage Vref1 or with a second reference voltageVref2, depending on the operating state of the circuit unit 3, in orderto produce the detector signal S2. In the exemplary embodiment, thisdetector signal S2 is supplied to the circuit unit 3 in order todisconnect the circuit unit 3 if the undervoltage detector detects anundervoltage between the connection terminals 11, 12. The level whichthe detector signal S2 assumes when such an undervoltage is detected issubsequently called the fault level. This fault level is dependent onthe circuit implementation and, in the case of the circuit shown in FIG.2, corresponds to a high level for the detector signal S2. The detectorsignal S2 can alternatively or additionally also be routed to theoutside, which is shown in dashes in FIG. 2, in order to supply it tofurther circuit arrangements (not shown).

The undervoltage detector shown compares the rms supply voltage V1 witha first reference value Vref1 during the first operating state of thecircuit unit 3 and with a smaller reference value Vref2 during a secondoperating state, in which the circuit unit 2 has an increased drawncurrent. During the first operating state, a drop in the supply voltageV1 below the first reference value Vref1 thus suffices to produce afault level for the detector signal S2, whereas during the secondoperating state the rms supply voltage V1 needs to drop below thesmaller reference value Vref2 in order to produce a fault level for thedetector signal S2. If the drawn current I3 in the circuit unit 3 rises,the voltage drop across the series resistor R increases and the rmssupply voltage V1 is reduced. Since the comparison threshold forproducing a fault level for the detector signal S2 is lowered in theinventive circuit arrangement during the second operating state, inwhich the circuit unit 3 has an increased drawn current, the increaseddrawn current during this second operating state does not erroneouslyresult in a fault level for the detector signal S2.

With reference to FIG. 2, the undervoltage detector 2 with thefunctionality explained has a comparator 21, one input (in the examplethe negative input) of which is supplied with the rms supply voltage V1and the other input (in the example the positive input) of which issupplied via a switch arrangement 22 either with the first referencevoltage Vref1 provided by a first reference voltage source 23 or withthe second reference voltage Vref2 provided by a second referencevoltage source 24. The switch arrangement 22, which changes over betweenthe two reference voltage sources 23, 24 is actuated by an operatingstate signal ST. This operating state signal ST represents the operatingstate of the load circuit unit 3 and can be produced in different waysdepending on the type of this circuit unit 3, as will be explainedbelow.

To provide the two reference voltages Vref1, Vref2, the undervoltagedetector shown in FIG. 2 has two reference voltage sources 23, 24, thesebeing merely representative of a multiplicity of differentimplementation options, however. A particularly simple-to-implementcircuit for providing two reference voltages Vref1, Vref2 is shown inFIG. 2. This circuit arrangement comprises a reference voltage source210, for example the bandgap circuit, which provides an output voltageVout. To produce this reference voltage Vout, the voltage source 210 issupplied with the rms supply voltage V1, for example. Connected betweenthe output of this voltage source 210 and reference-ground potential GNDis a series circuit comprising a plurality of, preferablytemperature-stable, resistors 211-214. In this case, different referencepotentials can be tapped off at the connecting node between two adjacentresistors in this series circuit. In the example, the second referencevoltage Vref2 can be tapped off across the resistor chain's resistor214, which is directly at reference-ground potential, while the firstreference voltage Vref1 can be tapped off across the series circuitcomprising this resistor 214 and the resistor 213, which is connecteddirectly adjacent thereto.

To explain a production option for the operating state signal ST, FIG. 4shows an exemplary embodiment of an integrated circuit arrangement inwhich the load circuit unit has a power MOSFET 33, a driver circuit 32for the power MOSFET 33 and a logic circuit 31 connected to the driver32. The driver circuit 32 is designed to convert a signal S31 which ispresent at the output of the logic circuit 31 into an actuation signalS32 with a level which is suitable for actuating the power MOSFET 33.This power MOSFET 33, whose drain and source connections can havecontact made with them from outside the integrated circuit 1 viaconnection terminals 14, 15, serves, by way of example, to operate aload Z which, for the purposes of illustration in FIG. 4, is connectedin series with the drain-source path of the power MOSFET 33 between aterminal for a load supply potential V++ and the power MOSFET. The loadsupply voltage V++ and the supply voltage V+ of the integrated circuitmay be either different voltages or the same voltages, depending on theload.

In the circuit shown in FIG. 4, the power MOSFET 33 is used as alow-side switch, that is to say that one of the connections of theMOSFET 33 is at negative supply potential or reference-ground potentialGND. It goes without saying that such a power MOSFET can also be used asa high-side switch, in which case the load is between the MOSFET and thereference-ground potential GND. The driver circuit 32 is matched to thedesired use of the MOSFET in the low-side or high-side switch, with theuse of the MOSFET 33 as a high-side switch in the driver 32 involving,by way of example, provision of a charge pump in order to be able toprovide a sufficiently high actuation potential on the gate connectionof the MOSFET 33.

Turning such a MOSFET on and off is sufficiently well known to requirecharge reversal in a gate-source capacitance Cgs provided internally inthe MOSFET, said capacitance being shown explicitly for the purpose ofbetter understanding in FIG. 4. When the MOSFET 33 is turned on, whichrequires the gate-source capacitance Cgs to be charged to a suitableactuation potential, a not inconsiderable charging current may berequired, depending on the size of this capacitance, which is deliveredby the driver power 32. This charging current which flows during theturned-on period can result in a not inconsiderable voltage drop acrossthe series resistor R and hence in a drop in the rms supply voltage V1.

The turning-on of the MOSFET 33 is prompted by an actuation signal S3,which is either produced internally in the integrated circuit by furthercircuit units (not shown in more detail) or which is supplied externallyby a further connection terminal. The load circuit unit 3 shown in FIG.4 always has an increased drawn current during the turn-on operation,that is to say while the gate-source capacitance Cgs is being charged toa suitable actuation potential, and this is equivalent to the secondoperating state of this switching unit. During the remaining period oftime, particularly also during the period of time during which thegate-source capacitance Cgs is being discharged to reference-groundpotential GND in order to turn off the MOSFET 33, the circuit unit 3 hasa lower drawn current, which is equivalent to the first operating statethereof.

In the circuit arrangement shown in FIG. 4, use is made of the fact thatthe second operating state, that is to say the increased drawn current,is initiated by the actuation signal S3. This actuation signal S3 istherefore supplied to the undervoltage detector 2 in order to producethe operating state signal ST. To produce the operating state signal ST,the undervoltage detector 2 has a timer 25, whose manner of operation isexplained below with reference to FIG. 5.

For the purposes of explanation, it will be assumed that this actuationsignal S1 assumes a high level at a time t1 in order to turn on theMOSFET 33 via logic unit 31 and the driver circuit 32. A changeoverperiod, that is to say the period of time during which the MOSFETchanges from the off to the on state and during which the drawn currentis increased, is prescribed particularly by the properties of the MOSFET33 and can be taken from datasheets for such components, in particular.

For a prescribed period of time after a rising edge of this actuationsignal S3, the comparator 21 is supplied with the smaller secondreference signal Vref2 for comparison with the rms supply voltage V1. Tothis end, for a prescribed period of time T1 after this rising edge, thetimer 25 produces a level for the state signal ST which prompts theswitching unit 23 to supply the second reference voltage Vref2 to thecomparator 21. In this case, this period of time T1 is preferably chosento be longer than the changeover period of the MOSFET 33, so that theincreased drawn current of the circuit unit 3 is at an end at this endof this period of time T1—when the first reference voltage Vref1 isadopted again. In this circuit arrangement shown in FIG. 4, the secondoperating state is thus ascertained indirectly via the actuation signalS3, which initiates this second operating state, and in knowledge of theperiod of time for which this second operating state is normallypresent, in order to produce the operating state signal ST. Besides thewaveform of the actuation signal S3 which is shown in FIG. 5 a, FIG. 5 bshows the waveform of the operating state signal ST derived from theactuation signal S3, and FIG. 5 c shows the waveform of the referencevoltage Vref applied to the second input of the comparator 21. Duringthe period of time Ti after the rising edge of the actuation signal S3,this reference voltage Vref corresponds to the second reference signalVref2 and otherwise to the first reference signal Vref1, as explained.

FIG. 6 shows a circuit implementation example of the timer 25 shown inFIG. 4. In this regard, the timer has an RS flipflop 251 whose Set inputS is supplied with the actuation signal S3 and whose reset input R issupplied with the actuation signal S3 after a delay via a delay element252. The output Q of this flipflop produces the operating state signalST. The flipflop 251 is set upon a rising edge of the actuation signalS3 in order to produce a high level for the state signal ST, and isreset following a time delay after this rising edge of the actuationsignal S3 in order to produce the low level for the operating statesignal ST. The period of time during which the operating state signal STis at a high level is dependent on the delay time of the delay element252. This delay time is chosen, with reference to the signal waveformsshown in FIG. 5, such that it corresponds to the period of time T1.

For the sake of completeness, it should be pointed out that the logicunit 31 can be designed, by way of example, to turn off the MOSFET 33via the driver circuit 32, regardless of the level of the actuationsignal S3, when the detector signal S2 is at a fault level, that is tosay when the rms supply voltage V1 drops below the first or secondreference value Vref1, Vref2, depending on the operating state of thecircuit unit 3. As indicated by the dashed arrows in FIG. 4, the logicunit 31 can be supplied not only with the actuation signal S3 and thedetector signal S2 but also with further control signals which areproduced by protective circuits (not shown in more detail) in the MOSFET33, such as an overtemperature protection circuit or an overvoltageprotection circuit. These control signals are used to actuate the MOSFET33 in suitable fashion when an exceptional state is detected by theprotective circuits explained, in order to protect a connected load orto prevent damage.

With reference to FIG. 8, a logic circuit 25_1 can also be provided,instead of the timer 25, in order to provide the status signal ST. Thislogic circuit 25_1 is supplied with a first control signal, whichindicates the start of the second operating state or an imminent changefrom the first to the second operating state, and with a second controlsignal, which indicates the end of the second operating state.

By way of example, the logic circuit 26 is a flipflop which is set bythe first control signal and is reset by the second control signal. Theoutput signal from this flipflop forms the operating state signal ST.

In this case, the first control signal may be the control signal S3which has already been explained beforehand. By way of example, thesecond control signal S4 can be produced by the power MOSFET 33 on thebasis of a load current. In the circuit shown in FIG. 4, it can beassumed that the operating state with increased drawn current in thecircuit 3 has concluded if the MOSFET 33 is on to such an extent thatits load current exceeds a prescribed threshold value. To produce thesecond control signal S4, it is thus sufficient to ascertain the loadcurrent with the prescribed threshold value.

To protect the power MOSFET from overload, it is usual to monitor theload current flowing through it permanently in order to disconnect theMOSFET in the event of an overload. A current-measurement signal whichis present anyway can then easily be used to produce the second controlsignal.

FIG. 7 shows an integrated circuit arrangement with an alternativesolution option for producing the operating state signal ST. The loadcircuit unit is shown merely schematically as a circuit block 3 in FIG.7, this circuit block being representative of any integrated circuitswhich can assume at least one first operating state or a secondoperating state and in which the drawn current of the two operatingstates is different.

To ascertain the operating state signal ST, this circuit arrangement isprovided with an operating state detector 4 which ascertains the drawncurrent in the circuit unit 3 by virtue of the input current I3 beingdetected by a current measuring arrangement 43. The resultantmeasurement signal S43 is compared with a reference signal Vref3, in theexample a reference voltage, using a comparator 41, in order to producethe operating state signal ST. In the example shown in FIG. 7, theoperating state signal ST assumes a high level if the drawn current I3is above a threshold value at which the current measurement signal S43is greater than the reference value Vref3. The switch arrangement 22 ischanged over independently of the operating state signal ST in themanner already explained by virtue of the comparator 21 being suppliedwith the first reference signal Vref1 during the operating state wherethe drawn current is small and with the second reference signal Vref2during the operating state where the drawn current is higher.

In summary, the inventive circuit arrangement involves an undervoltagefor a supply voltage supplied to the circuit arrangement being detectedon the basis of the operating state of a load circuit unit which issupplied with power by the supply voltage. In this case, the thresholdat which it is decided whether there is an undervoltage present islowered for operating states with increased drawn current in order thata drop in the supply voltage which results from a voltage drop across aseries resistor is not mistakenly detected as an erroneous undervoltage.In the inventive circuit arrangement, operational dips in the supplyvoltage are thus not detected as erroneous dips in this supply voltagewhich occur when a line is broken, for example. In addition, theinventive circuit arrangement may be provided with relatively largeexternal series resistors, which improves the protection for theintegrated circuit. Furthermore, the external storage capacitor(reference symbol C in the figures) may be implemented in a smaller formthan in conventional integrated circuits of this type.

LIST OF REFERENCE SYMBOLS

-   1 Integrated circuit arrangement-   4 Operating state detector-   11, 12 Connection terminals, supply voltage terminals-   14, 15 Load connection terminals of the MOSFET-   20 Undervoltage detector-   21 Comparator-   22 Switch arrangement-   23, 24 Reference voltage sources-   25 Timer-   30 Load circuit unit-   31 Logic unit-   32 Driver circuit-   33 Power MOSFET-   41 Comparator-   42 Reference voltage source-   43 Current measuring arrangement-   210 Reference voltage source-   214-211 Resistors-   251 RS flipflop-   252 Delay element-   C Buffer capacitor-   Cgs Gate-source capacitance-   GND Reference-ground potential-   I1 Input current for the integrated circuit arrangement-   I3 Input current for the load circuit unit-   R Resistor-   S2 Detector signal-   S3 Actuation signal-   S31, S32 Control signals-   ST Operating state signal-   V+ Supply voltage-   V++ Supply voltage for the load-   V1 rms supply voltage-   Vout Output voltage from the reference voltage source-   Vref1 First reference voltage, first reference value-   Vref2 Second reference voltage, second reference value-   Vref3 Reference value, reference voltage

1. An integrated circuit arrangement comprising: connection terminalsconfigured to receive a supply voltage, an undervoltage detector coupledbetween the connection terminals and configured to compare the supplyvoltage with a select reference value selected from a first referencevalue and a second reference value, the second reference value less thanthe first reference value, and to produce a detector signal on the basisof a result of the comparison, at least one circuit unit coupled betweenthe connection terminals, the at least one circuit unit including atleast one first operating state with a first drawn current and a secondoperating state with a second drawn current, the second drawn currentexceeding the first drawn current, wherein the select reference valuecorresponds to the first reference value during the first operatingstate, and corresponds to the second reference value during the secondreference state.
 2. The circuit arrangement as claimed in claim 1,wherein the undervoltage detector comprises: a comparator having a firstinput configured to receive the supply voltage, a second input and anoutput to which the detector signal is provided, a voltage sourcearrangement configured to provide first and second reference voltages, achangeover element coupled between the voltage source arrangement andthe second input of the comparator and which supplies the second inputwith the select reference value in the form of a select one of the firstand second reference voltages.
 3. The circuit arrangement of claim 2wherein the changeover element supplies the select reference valueresponsive to a switching signal.
 4. The circuit arrangement as claimedin claim 3, wherein an actuation signal influencing the operating stateof the at least one circuit unit is supplied to the undervoltagedetector in order to produce the switching signal.
 5. The circuitarrangement as claimed in claim 4, wherein the undervoltage detector isconfigured to compare the supply voltage with the second reference valueand otherwise with the first reference value for a prescribed period oftime after a prescribed edge of the actuation signal.
 6. The circuitarrangement as claimed in claim 4, wherein the at least one circuit unitincludes a switching unit.
 7. The circuit arrangement as claimed inclaim 6, wherein the switching unit includes a semiconductor switchingelement and a driver circuit for the semiconductor switching element,the driver circuit operable to turn the semiconductor switching elementon or off on the basis of the actuation signal.
 8. The circuitarrangement as claimed in claim 1, wherein the at least one circuit unitincludes a switching unit having a semiconductor switching element. 9.The circuit arrangement as claimed in claim 1, further comprising anoperating state detector coupled to the at least one circuit unit andwhich produces an operating state signal which is dependent on theoperating state and which is supplied to the undervoltage detector. 10.The circuit arrangement as claimed in claim 9, wherein the operatingstate detector is configured to determine an input current flowing intothe at least one switching unit and to provide the operating statesignal on the basis of the determined input current.
 11. An integratedcircuit arrangement comprising: connection terminals configured toreceive a supply voltage, a comparator having a first input configuredto receive the supply voltage, a second input and an output to which thedetector signal is provided, the second input configured to receive aselect reference voltage from a first reference voltage and a secondreference voltage, the second reference voltage less than the firstreference voltage, and to produce a detector signal on the basis of aresult of the comparison, at least switching circuit coupled between theconnection terminals and includes at least one first operating statewith a first drawn current and a second operating state with a seconddrawn current, the second drawn current exceeding the first drawncurrent, wherein the select reference voltage corresponds to the firstreference value during the first operating state, and corresponds to thesecond reference value during the second reference state.
 12. Thecircuit arrangement as claimed in claim 11, further comprising: avoltage source arrangement configured to provide first and secondreference voltages, a switching device coupled between the voltagesource arrangement and the second input of the comparator and whichsupplies the second input with the select reference voltage.
 13. Thecircuit arrangement as claimed in claim 12 wherein the switching devicesupplies the select reference voltage responsive to a switching signal.14. The circuit arrangement as claimed in claim 13, wherein theswitching signal corresponds to an actuation signal influencing theoperating state of the at least one switching circuit.
 15. The circuitarrangement as claimed in claim 14, further comprising a timer coupledto receive the actuation signal and configured to provide the switchingsignal based on the actuation signal.
 16. The circuit arrangement asclaimed in claim 15, wherein the timer is configured to generate theswitching signal such that the first reference voltage is supplied tothe second input of the comparator for a prescribed period of time aftera prescribed edge of the actuation signal.
 17. The circuit arrangementas claimed in claim 16, wherein the at least one switching circuitfurther includes a semiconductor switching element and a driver circuitfor the semiconductor switching element, the driver circuit operable toturn the semiconductor switching element on or off on the basis of theactuation signal.
 18. The circuit arrangement as claimed in claim 16,wherein the at least one switching circuit further includes asemiconductor switching element and a driver circuit for thesemiconductor switching element, the driver circuit operable to turn thesemiconductor switching element on or off on the basis of the actuationsignal.
 19. The circuit arrangement as claimed in claim 12, furthercomprising an operating state detector coupled to the at least oneswitching circuit and which produces an operating state signal which isdependent on the operating state and which is supplied to control theswitching device.
 20. The circuit arrangement as claimed in claim 19,wherein the operating state detector is configured to determine an inputcurrent flowing into the at least one switching circuit and to providethe operating state signal on the basis of the determined input current.